Options
20-GHz時脈倍頻單元設計與分析以0.18-um CMOS製程製作
Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-um CMOS Technology
Date Issued
2006
Date
2006
Author(s)
Wu, Sheng-Hann
DOI
en-US
Abstract
在這裡提出以0.18-um CMOS製程所製作20-GHz時脈倍頻單元, 應用於OC-768系統上, 採用雙迴路及三階濾波器以消除Jitter的影響. 所設計之電路達到輸出Jitter 0.2ps,rms及 4.5ps,pp同時在1.8V的偏壓下消耗40mW.
A 20-GHz clock multiplication unit for SONET OC-768 systems employs dual loops and third-order loop filter to suppress the jitter. Realized in 0.18-um CMOS technology, this circuit achieves an output jitter of 0.2 ps,rms and 4.5 ps,pp while consuming 40 mW from a 1.8-V supply.
Subjects
鎖相迴路
時脈倍頻單元
CMU
PLL
OC-768
Type
thesis
File(s)
No Thumbnail Available
Name
ntu-95-R93943080-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):b602c05223cf81d3abf8b7627bbf81a6