Analysis of Co-Synthesis Algorithms for Energy-Aware NoC Design

Network-on-Chip (NoC) has been proposed to overcome the complex on-chip communication problem of SoC (System-on-Chip) design in deep submicron. A complete NoC design contains exploration on both hardware and software architectures. The hardware architecture includes the selection of PEs (Processing Elements) with multiple types and their topology. The software architecture contains the allocation of tasks to PEs, scheduling of tasks and their communications. To find the best hardware design for the target tasks, both hardware and software architectures need to be considered simultaneously. Previous works on NoC design have proposed some co-synthesis algorithms, which minimizes energy consumption while meeting the real-time requirements commonly seen in the embedded applications. In this thesis, we compare the solution quality and running time of several types of co-synthesis algorithms including branch and bound algorithm, iteraitve algorithm and SA-based algorithm.