5~20 Gb/s Adaptive Linear Equalizer and Decision-Feedback Equalizer
Date Issued
2014
Date
2014
Author(s)
Lin, Yuan-Fu
Abstract
In recent years, in addition to the fast growing in data rate, wide-range data is also required in the applications of various multimedias and portable devices. As the data rate keeps rising, many significant problems appear. One is that the bandwidth is limited compared to the data rate. It will result a significant inter symbol interference (ISI) to degrade the bit error rate (BER). In order to deal with ISI, equalizers are widely adopted. However, the length or the material of the communication channel may be different depending on the application. Therefore, an adaptive algorithm with the equalizer is more popular in recent communication systems. In wide-range data rate application, power efficiency issue is also concerned.
This thesis is mainly divided into two parts. In Chapter 2, a 5-20 Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) architecture is proposed. We use a power scalable technique to improve the power efficiency for slow data rate. We also propose an adaptive algorithm using edge counting. This circuit is implemented in 40-nm CMOS process.
A 5-20 Gb/s adaptive charge-steering decision-feedback equalizer (DFE) is presented in chapter 3. To lower power consumption of the system, charge-steering logic circuit is adopted in this design. We use sign-sign least mean square (SSLMS) algorithm to adjust the DFE’s taps adaptively. This circuit is implemented in 40-nm CMOS process.
Subjects
線性等化器
決策回授等化器
低功率
可適性
Type
thesis
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