A programmable filter with self-tuning for DMT VDSL receiver
Resource
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
Journal
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
Pages
-
Date Issued
2002-08
Date
2002-08
Author(s)
Chou, Chia-Hua
Lin, Chien-Chih
Wang, Chorng-Kuang
DOI
N/A
Abstract
This paper presents a programmable filter with a self-tuning mechanism. Conformed with the DMT-VDSL (discrete multi-tone very-high-speed digital subscriber loop) system, the filter is configured as a 4-th order Chebyshev low-pass filter with programmable bandwidth in which the ripple is set to 0.5 dB. The cut-off frequencies are 1.104/spl times/2/sup n/ MHz, where n is 0, 1, 2, 3, 4, corresponding to different transmission rates. The filter is self-tuned by the proposed tuning mechanism that is based on the relation between DC and fundamental components of a filtered clock signal. Peak-and-valley detection is employed to observe the two frequency components in the time domain. Implemented in 0.35 /spl mu/m 1P4M digital CMOS technology, the circuit occupies an active area of 1.3/spl times/1.4 mm/sup 2/. According to the post-layout simulation, it achieves 55 dB THD using 2 V supply voltage while the output swing is 120 mV/sub pp/. The power consumption for the core filter is 2.8 mW, whereas the overall system, including the filter, the output buffer, and the tuning circuits, consumes 28 mW power.
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Type
journal article
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