LDPC Coding with Inter-block Memories
Date Issued
2005
Date
2005
Author(s)
Lu, Ming-Che
DOI
en-US
Abstract
As indicated in [12], we observe that a delay processor and a signal mapper following the encoder of a convolutional code C can result in a convolutional code C of large free distances. It is natural to consider once again applying a delay processor and a signal mapper to the output of the low-density parity check (LDPC) code to achieve large free distance.
With the proposed scheme, we show a design for a 2-level delay processor. And we proposed two decoding methods, ”original decoder” and ”iterative decoder”, in sec. 4.2
and sec. 5.1, respectively. Simulation results show that the performance of a 2-level delay processor with original decoder is good at moderate to high SNRs, but poor at low
SNR owing to the problem of the error propagation. To overcome this problem, iterative decoder was proposed. Simulation results show that the performance of a 2-level delay processor with iterative decoder is good not only at moderate to high SNR, but also at low SNR.
Subjects
低密度同位檢查碼
延遲處理器
遞迴解碼器
LDPC
Delay processor
Iterative decoder
Type
thesis
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