Automatic Test Pattern Generation for Delay Defects Using Timed Characteristic Functions
Date Issued
2014
Date
2014
Author(s)
Ho, Shin-Yann
Abstract
Automatic test pattern generation (ATPG) for delay defects is an essential quality control step in integrated circuit (IC) design flow. With feature dimensions shrinking and operation frequency increasing, small changes on circuit delay may seriously affect the circuit behavior. Delay faults are caused by the intrinsic imperfection of manufacturing process and may result in behavior deviation from correct operation. For high performance circuits, the influence of small delay defects (SDDs) is particularly significant. There are two kinds of prior ATPG methods, including timing-unaware and timing-aware ATPG. Timing-unaware ATPG is fast but can not provide high quality patterns for testing SDDs. Timing-aware ATPG addresses the shortcoming of timing-unaware ATPG, but is computationally too expensive for large circuits.
This thesis proposes a viable timing-aware ATPG method based on a satisfiability (SAT) formulation using timed characteristic functions (TCFs), which is considered as one of the fastest functional timing analysis (FTA) techniques. The approach can be applied on both combinational and sequential circuits. It provides a balanced trade-off between accuracy and efficiency. Experimental results show promising runtime and fault coverage improvements over prior SAT-based timing-aware ATPG methods. We also implement some enhancement techniques to improve ATPG efficiency and test quality. In addition, our method provides a nice complement to commercial tools in enhancing test quality.
Subjects
自動測資產生
延遲錯誤
功能性時序分析
布林可滿足性問題
小延遲缺陷
時間特徵函式
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-103-R01943091-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):675b72d05bd4780868737d44cf18e6f1