Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
Resource
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Journal
Custom Integrated Circuits Conference, 1994
Pages
-
Date Issued
1994-05
Date
1994-05
Author(s)
Kuo, J.B.
Su, K.W.
Lou, J.H.
Ma, Y.
Chen, S.S.
Chiang, C.S.
DOI
N/A
Abstract
This paper presents a device-level analysis of a BiPMOS pull-down structure for low-voltage dynamic BiCMOS logic gate circuit suitable for VLSI using sub-quarter-micron BiCMOS technology. Thanks to the BiPMOS pull-down structure, despite the slow turn-off of the bipolar device, the 1.5 V full-swing BiCMOS dynamic logic gate circuit shows a more than 1.8 times improvement in speed as compared to the CMOS static one.>
Type
journal article
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