A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3-μm LTPS-TFT Technology
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
56
Journal Issue
2
Pages
142-146
Date Issued
2009
Date
2009
Author(s)
Abstract
A phase-locked loop (PLL) with self-calibrated charge pumps (CPs) has been fabricated in a 3-μ low-temperature polysilicon thin-film transistor (LTPS-TFT) technology. A voltage scaler and self-calibrated CPs are used to reduce the static phase error, reference spur, and jitter of an LTPS-TFT PLL. This PLL operates from 5.6 to 10.5 MHz at a supply of 8.4 V. Its area is 18.9 mm2M, and it consumes 7.81 mW at 10.5 MHz. The measured static phase error without and with calibration is 80 and 6.56 ns, respectively, at 10.5 MHz. The measured peak-to-peak jitter without and with calibration is 3.573 and 2.834 ns, respectively. The measured reference spur is -26.04 and -30.2 dBc without and with calibration, respectively. The measured maximal locked time is 1.75 ms. © 2009 IEEE.
Subjects
Calibration; Charge pump (CP); Low-temperature polysilicon thin-film transistor (LTPS-TFT); Phase-locked loop (PLL)
Other Subjects
Calibration; Charge pump circuits; Field effect transistors; Jitter; Phase locked loops; Polysilicon; Temperature; Thin film circuits; Thin films; Voltage scaling; Charge pump; Low temperature poly-silicon thin-film transistors; LTPS-TFT; Peak-to-peak jitter; Phase Locked Loop (PLL); Reference spur; Static phase errors; Thin film transistors
Type
journal article
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