Code design and decoder implementation of low density parity check code
Resource
Emerging Information Technology Conference, 2005.
Journal
Emerging Information Technology Conference, 2005
Pages
-
Date Issued
2005-08
Date
2005-08
Author(s)
Ku, Mong-Kai
Li, Huan-Sheng
Chien, Yi-Hsing
DOI
N/A
Abstract
Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.
SDGs
Type
conference paper
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