Design of DLL-Based Programmable Clock Generator Using Differential Toggle-Pulse Latch
Date Issued
2009
Date
2009
Author(s)
Chen, Po-Hsun
Abstract
As the progress of the VLSI technologies, clock generator needed to mix a required clock as an operation of the synchronization or the degradation of the frequency, has been widely implemented in many applications of circuit systems, such as Microprocessor, Memory Integrated Chip, wireless communication. The ordinary structure of a clock generator could be classified into two kinds. One is phase-locked loop(PLL)；the other is delay-locked loop(DLL). The former one is usually adopted by conventional designer but DLL is more suggested because of its stability and easily designed architecture. Furthermore, DLL contents better performance of jitter. There are 12 choices of multiplication factors in the scheme we proposed. The newly circuits, such as enabled short-pulse generator(ESPG), differential toggle-pulsed latch(DTPL), are used to combine the multiphase of the DLL and generate the output clock. The output clock, which is fully differential output to increase the level of applications, wouldn’t be affected by the duty cycle of DLL’s multiphase. CMOS 0.18μm process is used in our work. The output frequency of the reference is between 150MHz to 1.8GHz from the input frequency 300MHz to 400MHz. The chip core area is 0.241mm x 0.316mm.
Subjects
Clock Generator
Delay-Locked Loop
Differential Toggle-Pulsed Ltach
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-98-R95943100-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):573f28e83eaad55c1794afbe549700e6