The Design and Analysis of Dual-Delay Path Ring Oscillators and a Multiphase Compensation Method for Fractional-N Frequency Synthesizers
Date Issued
2008
Date
2008
Author(s)
Chen, Zuow-Zun
Abstract
Ring oscillators and frequency synthesis are widely employed in communication systems, such as clock generators or in-loop modulators. In this thesis, a dual-delay path ring oscillator and a multiphase compensation method for fractional-N frequency synthesizer are covered.ing oscillators are widely used in clock generators and frequency synthesis. To increase the oscillation frequencies, dual-delay path ring oscillators are often implemented to explore the maximum frequency levels. Two oscillation modes have been found in differential four-stage dual-delay path ring oscillators, one named differential mode oscillation and the other named common mode oscillation. In differential mode oscillation, a single delay cell contains differential output waveforms, but in common mode, the output waveforms are in-phased. In addition, the oscillation frequencies of the two oscillation modes are not the same either. These problems might spoil the function of the clock generators and frequency synthesis. For more insight of dual-path ring oscillators, mathematical analysis and demonstrations including the two oscillation mode in a differential four-stage dual-delay path ring oscillator is presented. A differential four-stage dual-delay path ring oscillator is fabricated in a 0.18-um CMOS technology with an active area of 58?41 um2. The measured tuning range is from 1.77 GHz to 1.92 GHz in differential mode oscillation which consumes 13 mW from a 1.8-V power supply, and from 1.01 GHz to 1.055 GHz in common mode oscillation that consumes 10 mW from a 1.8-V power supply.igh performance frequency synthesis is required in communication systems such as WCDMA transceivers or in-loop modulation systems. In this thesis, a S-D fractional-N frequency synthesizer with a multiphase compensation method is proposed. To resolve the problem brought by nonidea effect such as delay unit mismatch and gain error, a proposed delay line structure and a digital control circuit including dynamic element matching techniques and a re-quantized S-D modulator is presented. A frequency synthesizer operating from 2.11 GHz to 2.17 GHz, is fabricated in a 0.18-um CMOS technology with an area of 0.92?1.15 mm2. Power consumption is 27.2 mW from 1.8-V power supply. The proposed architecture suppresses the quantization noise of 2.4-GHz output at 10-MHz frequency offset by 10 dB. The settling time is less than 25 usec.
Subjects
ring oscillator
delta-sigma modulator
fractional-N frequency synthesizers
phase-locked-loop (PLL)
frequency dividers
phase noise
quantization noise suppression
WCDMA.
Type
thesis
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