A K -band CMOS distributed doubler with current-reuse technique
Journal
IEEE Microwave and Wireless Components Letters
Journal Volume
19
Journal Volume
19
Journal Issue
5
Journal Issue
5
Pages
308-310
Start Page
308
End Page
310
ISSN
15311309
Date Issued
2009
Author(s)
Abstract
A K-band distributed frequency doubler is developed in 0.18 mum CMOS technology. This doubler combines the distributed topology for broadband characteristics and current-reuse technique to improve the conversion gain. The high-pass drain line and high-pass inter-stage matching network are used to obtain a good fundamental rejection. A measured conversion gain of better than -12.3 -dB is obtained, and the fundamental rejection is better than 30 dB for the output frequency between 18 and 26 GHz. The dc power consumption is 10.5 mW with a chip size of 0.55 times 0.5 mm 2 .
SDGs
Type
journal article