The Study of Split-Gate Non-Volatile Memory Technology
Date Issued
2005
Date
2005
Author(s)
Chu, Wen-Ting
DOI
en-US
Abstract
The study presented in this thesis is dedicated to split-gate non-volatile memory process technology improvement and cell characterization. A sharp poly-tip structure, generated by using a LOCOS-like approach is introduced to increase the electric field when the cell is erased using Fowler-Nordheim (F-N) tunneling through poly-poly oxide. The tunnel oxide charge trapping effect under various erase voltages is studied. When reading the cell in the linear region, it was found that the higher the erase voltage applied, the faster the cell current degraded, the greater the likelihood of charges being trapped in the oxide. By observing the F-N tunneling stress on floating gate (FG) connected devices, we also found that the higher the electric field across the oxide, the more the electrons are trapped. After 250O C baking, the oxide trapped charges created by the higher stress voltage are more difficult to heal than those created by a lower stress voltage.
A high source-coupling ratio design for full-featured EEPROM composed of one-transistor split-gate cells with a cell area of less than 22F2 is first proposed in this study. This is in contrast to a traditional cell that requires an extra select-transistor and is not effective for cell size when compared to the new design cell. In this design, an inhibited source voltage is used for the unselected cell to achieve bit erase. It has demonstrated excellent program and erase disturb margins and has passed a 300k program/erase (P/E) cycling test. It was found that after the P/E cycling stress, the cell gains a better erase disturb immunity.
A p-channel split-gate flash memory cell, employing a field-enhanced structure, is also demonstrated in this study. The erase voltage is as low as 12 V. In cell programming, both channel-hot-hole impact ionization induced channel-hot-electrons (CHE) and band-to-band tunneling induced hot electrons (BBHE) are evaluated. BBHE shows an injection efficiency of ~2 orders in magnitude higher than that of CHE. The cell also demonstrated an acceptable program disturb window, which is of high concern in a p-channel stacked-gate cell. Both programming approaches can pass 300k P/E cycles.
During poly oxidation, the bird’s beak encroaches under the SiN film, especially along the poly grain boundary, causing non-uniform FG spacing, even bridging, which is an obstacle to cell shrinkage. We proposed an ammonia treatment on the poly to nitridize the poly surface, thereby avoiding bird’s beak bridging. After the ammonia treatment, FG spacing is quite uniform and can be improved from 0.09 mm to 0.03 mm. The XPS analysis on the ammonia treated poly shows the oxynitride thickness is less than 5 nm.
A shrinkable triple self-aligned split-gate flash cell fabricated using a 0.13-mm copper interconnect process is firstly demonstrated in this study. The approach used here to create a self-aligned structure is to form a spacer against the prior layer. Due to a higher aspect ratio when the cell pitch decreases, the profile of the spacer structure becomes sharper. This improves process control of the spacer profile and length. All processes used here are compatible with standard logic process. The word line channel length of the cell is 0.11 mm. The cell area is comparable to that of a stacked-gate cell and can be less than 13F2. Characterization shows considerable program and erase speed, up to 300k P/E cycles, and excellent disturb margins.
Subjects
分離式閘極
自我對準
多晶矽尖角
非揮發性記憶體
快閃記憶體
field-enhanced structure
disturb
flash
split-gate
source-coupling
full-feature EEPROM
p-channel
self-aligned
Type
thesis
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