Issues and support for dynamic register allocation
Journal
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Journal Volume
4186 LNCS
Pages
351-358
Date Issued
2006
Author(s)
Abstract
Post-link and dynamic optimizations have become important to achieve program performance. A major challenge in post-link and dynamic optimizations is the acquisition of registers for inserting optimization code in the main program. It is difficult to achieve both correctness and transparency when software-only schemes for acquiring registers are used, as described in [1]. We propose an architecture feature that builds upon existing hardware for stacked register allocation on the Itanium processor. The hardware impact of this feature is minimal, while simultaneously allowing post-link and dynamic optimization systems to obtain registers for optimization in a "safe" manner, thus preserving the transparency and improving the performance of these systems. © Springer-Verlag Berlin Heidelberg 2006.
Other Subjects
Computer hardware; Optimization; Program processors; Resource allocation; Dynamic optimizations; Dynamic register allocation; Inserting optimization code; Computer architecture
Type
book