A 2.89mW 50GOPS 16 × 16 16-core MIMO sphere decoder in 90nm CMOS
Journal
ESSCIRC 2009 - 35th European Solid-State Circuits Conference
Pages
344-347
Date Issued
2009
Author(s)
Abstract
A 16-core multi-input multi-output (MIMO) decoder for agile communication systems is implemented in a low-V T 90nm CMOS technology. This chip implements the sphere decoding algorithm and is highly flexible to support multiple configurations: antenna arrays from 2×2 to 16×16, modulations from BPSK to 64QAM, and up to 128 data streams. Operating at 16MHz, the chip provides 50GOPS (12-bit add equivalent) in the 16×16, 64QAM mode. It consumes 2.89mW of power with a 321mV supply voltage, resulting in a power efficiency of 17.3GOPS/mW. At 256MHz, the peak data rate exceeds 1.5Gbps over a 16MHz channel.
SDGs
Type
conference paper