A Spur Cancellation Technique for Digital Multiplying Delay-Locked Loops

A digital multiplying delay-locked loops (DMDLL) with a reference spur cancellation technique is presented. At the first, the problem of serious reference spur caused by conventional multiplying delay-locked loops (MDLL) is discussed. By detecting the static phase offset between the reference-signal path and inject-signal path, a negative feedback loop is used to compensate the phase error. Beside, unlike conventional MDLL capture the phase of the process, a digital phase-locked loop (DPLL) is commonly used for the proposed DMDLL, can be switched automatically according to instant frequency variation, no additional reset signal. The proposed DMDLL is implemented in the Verilog language and simulated with ISim simulator. The reference frequency and the output frequency have been set to 40 MHz and 1.6 GHz, respectively. The spur can be pulled down to -100 dB/Hz less than -65 dB/Hz caused by MDLL without the cancellation technique. The root-mean-square jitter is 1.28 ps.