A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback
Journal
Midwest Symposium on Circuits and Systems
ISBN
9798350302103
Date Issued
2023-01-01
Author(s)
Wu, Jun Yi
Abstract
This paper addresses the issues associated with multi-bit CT-DSM to significantly increase the number of bits within. A system architecture of CT-DSM, suitable for multi-bit quantizers and high-resolution feedback, is proposed. The employment of high-resolution feedback in CT-DSM improves stability, reduces the linearity requirements and power consumption of the amplifiers, and mitigates clock jitter sensitivity. A CT-DSM ADC utilizing 9-bit feedback DAC is presented. The proposed active-RC proportional-integrator-based loop filter, hybrid switched resistor-DAC, and an optimized metal-oxide-metal capacitor allow for an efficient design of highly multi-bit CT-DSM, thereby achieving low power consumption. The prototype chip is fabricated in TSMC 28nm CMOS process and occupies an active area of 0.063mm2. Clocked at 40 MHz, the modulator measures a 74.9 dB SNDR and 76.4 dB dynamic range within a 1.25 MHz bandwidth while consuming only 0.36mW from a single 0.9V supply, achieving a FOMs and FOMw of 170.4 dB and 32.2 fJ/conversion-step., respectively.
Subjects
analog-to-digital converter | continuous-time delta-sigma modulator | error feedback | mismatch shaping | successive-approximation-register
SDGs
Type
conference paper