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  4. The demonstration of Carbon Nano-Tubes (CNTs) as a promising high Aspect Ratio (>25) through Silicon Vias (TSVs) material for the vertical connection in the high dense 3DICs
 
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The demonstration of Carbon Nano-Tubes (CNTs) as a promising high Aspect Ratio (>25) through Silicon Vias (TSVs) material for the vertical connection in the high dense 3DICs

Journal
Technical Digest - International Electron Devices Meeting, IEDM
Journal Volume
2020-December
Pages
12.6.1-12.6.4
Date Issued
2020
Author(s)
Lu P.-Y
Yen C.-M
Chang S.-Y
Feng Y.-J
Lien C
Hu C.-W
Yao C.-W
Lee M.-H
Liao M.-H.
MING-HAN LIAO  
DOI
10.1109/IEDM13553.2020.9371949
URI
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85102939120&doi=10.1109%2fIEDM13553.2020.9371949&partnerID=40&md5=0f801b38e978a8e3a93c46c69b859b56
https://scholars.lib.ntu.edu.tw/handle/123456789/576187
Abstract
With the excellent material properties of Carbon Nano-tubes (CNTs) developed in this work (Coefficient of Thermal Expansion~-2 x 10-6 K-1, Resistivity~10-6 Ω-m, Young's modulus~1000 GPa, and thermal conductivity ~800 Wm-1K-1), the real 3D integrated circuits (ICs) system with CNTs as the high aspect ratio (>25)/small diameters (<5 μm) Through Silicon Vias (TSVs) is demonstrated. The device temperature can be reduced ~15 °C and the keep-out zone region can be reduced ~80%. on the other hand, the CNTs 3DICs system also shows that the better system-level electrical performance from the latency, bandwidth density, power density, and reliability (~10X) points of view. The developed technologies including (1) High quality CNTs growing at the low temperature (550 °C) using a novel gas Fe(C5H5)2 reactant, (2) Optimized wafer bonding process, (3) Non-mask laser engrave patterning, and (4) wafer transfer technology by a thermal release tape/ethylene viny acetate processes provide the useful solution for the applications of CNTs as a vertical connection material in the near coming high-density 3D device. ? 2020 IEEE.
Subjects
Aspect ratio; Carbon nanotubes; Elastic moduli; Electron devices; Electronics packaging; Integrated circuit interconnects; Iron compounds; Laser materials processing; Silicon wafers; Temperature; Thermal conductivity; Thermal expansion; Wafer bonding; 3d integrated circuit (ICs); Carbon nano tube (CNTs); Device temperature; Electrical performance; High aspect ratio; Through silicon vias; Wafer bonding process; Wafer transfer technologies; Three dimensional integrated circuits
Type
conference paper

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