Reducing Conflict Misses on Partition Cache
Date Issued
2004
Date
2004
Author(s)
Lin, Hsiu-Ping
DOI
en-US
Abstract
We observe that the average percentage of conflict misses to all cache misses is quite high from the simulation results. In general, the average percentage of conflict misses is roughly 30%-99% in direct-mapped caches and most of them are much higher than low bound. In 2-way set-associated caches, the average percentage of conflict misses is roughly 20%-95% while most of them are near to low bound. As a result, we propose a new schema “partition cache” applied to traditional direct-mapped and 2-way set-associated caches, and we call them “partition direct-mapped caches” and “partition 2-way set-associated caches”, respectively. They can reduce conflict misses efficiently compared with conventional cache architecture. The average reduction of conflict misses is 10%-98% generally. Furthermore, with slight hardware and execution time overheads, our new schema also improves performance significantly, which is resulted from reducing conflict misses efficiently. From the simulation results, the performance improvement is 10%-95% generally, and the performance improvement is especially obvious in instruction caches. In general, the performance improvement of partition direct-mapped caches is better than that of partition 2-way set-associated caches.
In addition, our schema is lower power consumption compared with conventional cache architecture. This is because the power consumption per access of the partition cache is only dependent on partition size.
In addition, our schema is lower power consumption compared with conventional cache architecture. This is because the power consumption per access of the partition cache is only dependent on partition size.
Subjects
快取記憶體
碰撞失敗
conflict misses
cache
cache misses
SDGs
Type
thesis
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