A Priority Based Method for Output Arbiter on etwork-on-Chip Router
Date Issued
2009
Date
2009
Author(s)
Chan, Cheng-Hao
Abstract
With the development of deep submicron chip technology, a chip can pack more than a billion transistors nowadays. This capacity will allow the System-on-Chip (SoC) designs with a large amount of IP cores on a single chip. However, the inter-communication between IP cores becomes a new challenge. In recent years, Network-on-Chip (NoC) has been proposed to provide an on-chip communication infrastructure with better scalability and reliability. The 2D mesh is a very popular topology of previous NoC designs, because of the simplicity with designing its routing algorithm and network scalability. The low latency design is one of the most important issues to Network-on-Chip design and the implement of scalable communication structures. The congestion delay is the most important issue of latency. In this thesis, we propose a priority based output arbitration method to eliminate the congestion states of the NoC. By detecting and dispatching the packet requirements from different directions, the packets have different priorities. According to the priorities, the packets can pass the congested router in order. Simulation results demonstrate that the proposed method can reduce the transmission latency about 20% in uniformly distributed traffic and about 30% in hot-spot traffic in saturation point when compared with the conventional router. Moreover, in VOPD traffic, the proposed method can reduce latency more than 10% when the injection rate is greater than 11 (flits/nodes/cycle). In the router design, the new arbiter area overhead is less than 1%.
Subjects
Network-on-Chip
System-on-Chip
Network congestion
Output Arbiter
SDGs
Type
thesis
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