Automatic Loop Gain Optimization for Digital Phase-Locked Loops
Date Issued
2015
Date
2015
Author(s)
Kuan, Ting-Kuei
Abstract
Since 1930s, phase-locked loops (PLLs) have been widely employed in radio, telecommunications, computers and other electronic devices. Specifically, they can be used to generate well-timed clocks for a variety of applications such as clock and data recovery (CDR), microprocessor clock generation, and wireline transmitters. In designing the PLLs, fundamental but quite important questions always arise: “What is the optimal loop gain for a PLL system to achieve the best jitter performance?” and “Can this optimal loop gain be automatically attained in background to tolerate process and environment variations?” Unfortunately, the theory of the automatic loop gain optimization technique has not been revealed so far. This thesis presents the theory and the practice of the automatic loop gain optimization technique for digital PLLs (DPLLs) to breakthrough that traditional barrier. The DPLLs are often classified into two types with respect to their phase detector: a time-to-digital converter (TDC) or a bang-bang phase detector (BBPD), and this thesis will discuss both two types in two chapters. Chapter 1 highlights the contributions of this thesis to the world. Chapter 2 demonstrated the loop gain optimization technique for TDC-based DPLLs. Chapter 3 demonstrated the loop gain optimization technique for digital bang-bang PLLs (DBPLLs). In addition, the gain of the nonlinear BBPD is derived, taking into account the external and the internal noise sources simultaneously (different from the conventional approach). The multi-rate noise model is constructed to investigate the cyclostationary phenomenon of the PLLs, which reveals undisclosed secrets. A DBPLL using the automatic loop gain optimization and the loop latency reduction techniques is implemented. The chip was fabricated in TSMC 40nm CMOS Technology. Finally, the conclusion and the future work are drawn in Chapter 4.
Subjects
Digital Phase-Locked Loop
Phase-Locked Loop
Bandwidth
Loop Gain
Optimization
Clock Jitter
Noise
Automatic Calibration
Process Variation
Voltage Variation
Temperature Variation
PVT Variations
Multi-Rate Noise Model
Type
thesis