ReSSP: A 5.877 TOPS/W reconfigurable smart-camera stream processor
Journal
Proceedings of the Custom Integrated Circuits Conference
Date Issued
2011
Author(s)
Abstract
A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor is implemented in 90nm CMOS technology. A reconfigurable hardware architecture with heterogeneous stream processing and subword-level parallelism is implemented to accelerate the vision processing for smart-camera applications. The area efficiency reaches 111.329 GOPS/mm2. The power efficiency and area efficiency are 4.5x to 33.0x and 3.8x to 74.2x better than the state-of-the-art works, respectively. © 2011 IEEE.
Event(s)
33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011
Other Subjects
90nm CMOS; Area efficiency; Power efficiency; Re-configurable; Smart-camera; Stream processing; Stream processor; Vision processing; Cameras; CMOS integrated circuits; Computer hardware description languages; Efficiency; Integrated circuit manufacture; Integrated circuits; Reconfigurable hardware
Type
conference paper