A 3.6-GHz Quantization Noise Cancellation Fractional-N ADPLL using Time-Division Multiplexing TDC
Date Issued
2014
Date
2014
Author(s)
Sheng, Yun-Chen
Abstract
A 3.6-GHz quantization noise cancellation fractional-N ADPLL using time-division multiplexing time-to-digital converter (TDM TDC) is presented. With quantization noise cancellation technique, quantization noise from delta-sigma modulator (DSM) can be greatly reduced. In a conventional approach, a gain calibration loop is adopted to estimate cancellation gain factor, and thus PLL lock time is degraded. With the proposed TDM TDC, no gain calibration is required. TDM TDC achieves fast and accurate cancellation gain estimation, and PLL lock time is not degraded as that of a conventional approach. The proposed technique is implemented in the design of a 3.6-GHz ADPLL. Fabricated in the TSMC 90-nm CMOS technology, the whole system dissipates 8.16 mA from a 1.2-V supply and the active area is 0.329 mm2. At 3.6 GHz, the reference spur at 26 MHz offset is -45 dBc and the phase noise measured at 10-MHz offset is reduced from -99.79 dBc/Hz to -123.44 dBc/Hz, corresponding to 23-dB improvement. RMS jitter integrated from 10 kHz to 40 MHz is reduced from 10.88 ps to 4.605 ps. The measured lock time of the proposed ADPLL is 6 μs.
Subjects
ll-Digital Fractional-N Frequency Synthesizer
Quantization Noise
Time-to-Digital Converter
Phase-Locked Loop
Type
thesis
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ntu-103-R01943029-1.pdf
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