50+Gb/s Transceivers for Next Generation Ethernet Systems
Date Issued
2015
Date
2015
Author(s)
Chiang, Ping-Chuan
Abstract
The ever-growing volume of Ethernet has pushed the backbone network data rate from Mb/s to tens or hundreds of Gb/s in past decades. The core network data rate in backbone averagely doubles every 1.5 years, which is even faster than the data rate improvement of server I/Os (2× every two years). The 100-Gb/s Ethernet (100GbE) must deal with several difficulties, which are less serious or do not exist at all in older standards. The first part of this thesis provides a broad and deep description of the 100GbE chipset in transistor level with theoretical analysis. It consists of a 4-lane laser-diode driver (LDD) array, and a 4-lane transimpedance amplifier/limiting amplifier (TIA/LA) array. Optical components are characterized and modeled as well. Modern standards such as 100-Gb/s Ethernet (100GbE) will soon become mainstream products. However, in next generation’s 400-Gb/s Ethernet systems, we may need 8-lane data channels, and each of them delivers 50-Gb/s data in NRZ or PAM4 format. Short-distance applications such as backplane and chip-to-chip data links have similar approaches. The second part in this thesis illustrates the design of a 56-Gb/s PAM-4 transceiver. The TX adopts half-rate feed-forward equalizer (FFE) with pre-distortion driver to achieve 9-dB maximum boosting and 100% linearity control, which can compensate the non-linearity of modern electroabsorption-modulated laser (EML). The third part in this thesis illustrates a CMOS CDR design shooting for NRZ data format with data rate beyond 50 Gb/s. Before 2014, no CMOS clock and data recovery (CDR) circuit has been proven at such a high data rate. In this part, we present a NRZ receiver incorporates a unique technique to extract clock from the ultra high-speed data stream and demultiplex it by a factor of 8. The design difficulty for individual blocks and the whole integrated system has been reported with explanation and discussion.
Subjects
100Gb/s Ethernet
clock and data recovery
laser diode driver
transceiver
Type
thesis