Multilayer nucleation at step walls: a low-barrier pathway for polytype control in SiC crystal growth
Journal
Journal of Crystal Growth
Journal Volume
680
Start Page
128502
ISSN
00220248
Date Issued
2026-04-01
Author(s)
Abstract
Unwanted polytype inclusions, such as 6H in 4H-SiC during physical vapor transport (PVT) or 4H in 3C-SiC during high-temperature solution growth (HTSG), pose significant challenges in SiC crystal growth for power electronics applications. Although prevailing studies highlight large-terrace two-dimensional (2D) nucleation under high supersaturation as the primary mechanism for polytype transitions, this does not fully explain inclusions at low driving forces. Here, we introduce a complementary low-barrier pathway inspired by multilayer twinning in silicon: a multilayer nucleation model at step-wall/terrace corners, governed by the interfacial wall affinity (Δγe, representing the energy reduction relative to the wall/fluid interface) and polytype energy penalty (σpoly). By linking the effective driving force Δgeff to supersaturation (S) and undercooling (ΔT), we integrate our model with classical 2D nucleation theory. Results demonstrate that macro-steps enable multilayer embryos to amortize stacking penalties through layer-by-layer energy redistribution, facilitating foreign polytype nucleation at substantially lower supersaturation. This step-wall-mediated mechanism accounts for polytype inclusions under low driving forces, bridging gaps in terrace-based models. Proposed strategies to mitigate inclusions include minimizing macro-steps and tuning wall affinity via doping to elevate barriers, as validated by recent Al-doping experiments, offering a robust framework for precise polytype control and defect reduction in high-performance SiC crystal growth.
Subjects
High-temperature solution growth
Multilayer nucleation
Physical vapor transport
Polytype control
Silicon carbide
Step-wall nucleation
Supersaturation
Publisher
Elsevier B.V.
Type
journal article