A 4.8-mW Hybrid Crypto SoC With Post-Quantum Cryptography and Lightweight Cryptography for Secure Neural Interfacing
Journal
IEEE Journal of Solid-State Circuits
Start Page
1-11
ISSN
0018-9200
1558-173X
Date Issued
2025
Author(s)
Abstract
This work presents the first hybrid crypto systemon- chip (SoC) for secure neural interfacing based on postquantum cryptography (PQC) and lightweight cryptography (LWC). The transmitted signals are protected through a two-stage hybrid cryptosystem, in which handshake and data encryption are protected by PQC and LWC, respectively. Algorithms are well explored for PQC and LWC, including Falcon digital signature algorithm (DSA), NTRU key encapsulation mechanism (KEM), and ASCON authenticated encryption (AE). Hardware cost is minimized through algorithm-architecture optimizations, including serial-based number theoretic transform (NTT), integrated polynomial multiplication, MK modular multiplication, and shuffing-based fixed-type polynomial sampling. Fabricated in 40-nm CMOS, the SoC integrates 921 K logic gates in core area of 0.62 mm2. The chip supports post-quantum secure neural interfacing for various data formats. The power consumption is 4.8 mW at 50 MHz from a 0.7 V supply. This chip consumes 0:7 μJ/OP and 48 pJ/B for the PQC handshake and LWC data encryption, respectively. Compared to the state-of-the-art designs, the SoC dissipates 12-to-46× less energy and achieves 1.3-to- 168× higher area efficiency for the handshake, and dissipates 7× less energy and achieves 3× higher area efficiency for data encryption.
SDGs
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article