A 12.6mW 573-2,901KS/s Reconfigurable Processor for Reconstruction of Compressively-Sensed Physiological Signals
Journal
Int. Symposium on VLSI Circuits (VLSI Circuits)
Date Issued
2018
Author(s)
Abstract
This work presents a reconfigurable processor based on the alternating direction method of multipliers (ADMM) algorithm for reconstructing compressively-sensed signals. The chip delivers a throughput of 573-to-2,901KS/s for reconstructing physiological signals. It dissipates 12.6mW at 87 MHz at 0.6V. Compared to the state-of-the-art designs, the chip achieves a 5.7-to-14x higher throughput with 5-to-11x lower energy for the target reconstruction SNR (RSNR) ≥ 15dB.
SDGs
Type
conference paper