VLSI Implementation of a Reconfigurable Soft-output MIMO Detector Using a Novel Sphere Decoding Algorithm
Date Issued
2009
Date
2009
Author(s)
Liao, Chun-Hao
Abstract
In this work, VLSI implementation of a configurable, soft-output MIMO detector is presented. The proposed IC can support up to 8?8 64QAM spatial multiplexing MIMO communications, which surpasses all reported MIMO detector ICs in antenna number and modulation order. Moreover, this chip provides configurable antenna number from 2?2 up to 8?8 and modulation order from QPSK to 64QAM. Its outputs include bit-wise log likelihood ratios (LLRs) and a candidate list, making it compatible with powerful soft-input decoders and iterative decoders. The MIMO detector adopts a novel sphere decoding algorithm with high decoding efficiency and better error rate performance, called modified best first with fast descent (MBF-FD). Moreover, a low-power pipelined quad-DEAP circuit for efficient node pool management and several circuit techniques are implemented in this chip. When this IC is configured as 4?4 64 QAM and 8?8 64QAM soft-output MIMO detectors, it achieves average throughputs of 297Mbps and 207.1Mbps with only 58.2mW and 74.8mW respective power consumption and negligible performance degradation (less than 0.1dB in SNR).
Subjects
Wireless communication
Multiple-input multiple-output system (MIMO)
Sphere decoding
Type
thesis
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