A Spur Suppression Technique for Phase-Locked Frequency Synthesizers
Date Issued
2006
Date
2006
Author(s)
Lee, Wei-Liang
DOI
en-US
Abstract
With the rapid growing of the wireless communication system, the demands of high precision, low power and fast settling time phase-locked loops (PLLs) increase significantly. The design of PLL generally deals with a tight tradeoff between the settling time and the magnitude of the reference sidebands that appears at the PLL output. This tradeoff limits the performance and leaves very little freedom to design a phase-locked frequency synthesizer.
In this thesis, we introduce an architecture with distributed phase frequency detectors (PFDs) /charge pumps (CPs) for integer-N frequency synthesizer to reduce the magnitude of the reference spur significantly without changing the loop parameters. To suppress the nonidealities of the open-loop delay lines used in the proposed architecture, pulse-position modulation (PPM) technique is adopted to modulate the positions of ripples on the control line and spread the spur power, decreasing the magnitude of the reference sideband further.
A 4.8-GHz phase-locked frequency synthesizer with four distributed PFDs/CPs and PPM is designed and fabricated in TSMC 0.18-μm CMOS technology. The chip size is 1 mm × 0.9 mm. The experimental result shows that the proposed architecture can reduce the spur magnitude by 10 dB, compared with the conventional architecture, while dissipating only 10 mA from a 1.8-V power supply. The phase noise of the 2.4-GHz output is -110 dBc/Hz at 1-MHz offset.
Subjects
鎖相迴路
頻率合成器
脈衝位置調變
PLL
frequency synthesizer
PPM
Type
thesis
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