A DfT Technique for Rise Time and Fall Time Testing of LCD Source Driver IC
Date Issued
2008
Date
2008
Author(s)
Lin, Chih-He
Abstract
This thesis presents a DFT technique to measure the rise/fall time and the offset of TFT-LCD source driver IC. The proposed DFT performs on-chip voltage comparison in parallel so the required number of tester channels <pins> is greatly reduced. According to simulation results, the accuracy of offset testing is 2mV and the rise/fall tine testing is 100ns. The proposed technique saves hundreds of I/O pins and reduces the total test time by 40%. Although the area penalty is 10%, the DFT circuitry is implemented on the scribe line so it is non-intrusive to the original design. The DFT has been implemented on an industrial design in 0.18μm technology.
Subjects
DfT
Source driver
rise time
fall time
Type
thesis
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