CMOS four-quadrant multiplier using active attenuators
Journal
International Journal of Electronics
Journal Volume
79
Journal Issue
3
Pages
323-328
Date Issued
1995
Author(s)
Chang, C.-C.
Abstract
A new CMOS four-quadrant multiplier using active attenuators is presented. Simulation results show that for a power supply of ±5 V, the linear range is over + 1 V with the linearity error less than 0-83%. The total harmonic distortion is less than 1% with an input range up to ± 1 V. The simulated —3dB bandwidth is about 5 MHz. Experimental results show that the linear range is within ± 1 V. The proposed multiplier is expected to be useful in analogue signal processing applications. © 1995 Taylor & Francis Ltd.
SDGs
Other Subjects
Electric attenuators; Error analysis; Integrated circuit layout; Mathematical models; Multiplying circuits; Numerical analysis; Signal distortion; Active attenuators; Analogue signal processing; Four quadrant multiplier; Harmonic distortion; Linearity error; CMOS integrated circuits
Type
journal article