High Speed FPGA-based Hardware Implementation of 3D Video Optimization for Human Visual Comfort Enhancement
Date Issued
2012
Date
2012
Author(s)
Lin, Chi-Ping
Abstract
Stereo video can make users sense depth perception by showing two frames to each eye simultaneously. It can give users vivid information about the scene structure. However, to provide a comfortable view experience on 3DTV must become the main topic.
In this thesis, we analyze the visual fatigue reason by the human factor experiments firstly. The depth information will do major impact on the human visual system. It must be controlled in an appropriate range. Secondly, we utilize the geometry model to obtain the transformation between 3D (object space) and 2D (screen space). Besides, the relation between depth (parallax) and camera parameters was revealed by going deep into the model. We use Disparity Estimation (DE) to search the difference among the two frames. It will export disparity maps for frames rendering. Then, Depth Image Base Rendering (DIBR) which merged the relation is used to reconstruct the modified frames.
In order to process the stereo video with the huge amounts of data, the FPGA boards (CVK) we chose includes SDRAMs which are with large capacity. Another reason is to suit the HDMI standard transmission. The point of hardware implementation is the architecture design for the two reasons. The architecture of our system can display algorithm result through HDMI signal. It also represent the SDRAMs are successfully accessed.
The system on FPGA board can achieve 1.72 frames per second (fps) in 1080p display format, with DE search range of [-15,+14] in horizontal direction. Registers count is 6.844K. LUTs count is 9.339K. Logic count is 8.859K. The SRAM size is 30K bits.
Subjects
Stereo and 3D
binocular parallax
disparity estimation
depth image base rendering (DIBR)
FPGA
SDRAM
HDMI
Type
thesis
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