WiT: Optimal wiring topology for electromigration avoidance
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
20
Journal Issue
4
Pages
581-592
Date Issued
2012
Author(s)
Abstract
Due to excessive current densities, electromigration (EM) may trigger a permanent open- or short-circuit failure in signal wires or power networks in analog or mixed-signal circuits. As the feature size keeps shrinking, this effect becomes a key reliability concern. Hence, in this paper, we focus on wiring topology generation for avoiding EM at the routing stage. Prior works tended towards heuristics; on the contrary, we first claim this problem belongs to class P instead of class NP-hard. Our breakthrough is, via the proof of the greedy-choice property, we successfully model this problem on a multi-source multi-sink flow network and then solve it by a strongly polynomial time algorithm. Experimental results prove the effectiveness and efficiency of our algorithm. © 2006 IEEE.
Subjects
Algorithms; electromigration (EM); global routing; integrated circuit reliability; linear programming
Type
conference paper