A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example
Date Issued
2006
Date
2006
Author(s)
Tsai, Chin Feng
DOI
zh-TW
Abstract
Aiming to a mixed software/hardware system, in this thesis, we make use of the platform-based methodology to design hardware accelerators on FPGAs. We focused on reducing the hardware/software communication overheads in partitioning the codes. We design three kinds of hardware accelerators on FPGAs and discuss how to measure communication costs. The result of the measurement is then used to divide the codes in a hardware/software that enhances the performances of software. Finally we analyze the performances of our designs.
Subjects
混合軟硬體系統
基於平台硬體加速器設計方法
硬體加速器
溝通花費
mixed software/hardware system
platform-based methodology
hardware accelerators
commutation cost
Type
thesis
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