Digital VLSI OFDM transceiver architecture for wireless SoC design
Resource
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Journal
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Pages
-
Date Issued
2005-05
Date
2005-05
Author(s)
Tseng, Wei-Hsiang
Chang, Ching-Chi
Wang, Chorng-Kuang
DOI
N/A
Abstract
This paper presents the VLSI architecture of an OFDM baseband transceiver for wireless communications. The open/closed-loop carrier recovery achieves the stepping frequency acquisition for high-band RF systems, and the proposed timing recovery cooperating with the self-correcting interpolation realizes an OFDM baseband digital IP design. Hardware sharing and power-of-2 coefficients fulfill this compact transceiver system chip. Simulations show that the receiver can deliver 10% packet error rate (PER) requirement under all specified SNR for IEEE 802.11a. Using the typical 0.25 micrometre CMOS technology, the chip occupies 3.5/spl times/3.5 mm/sup 2/ area and consumes 109 mW under 2.5 V power supply.
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Type
journal article
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