VLSI architecture for radix-2k Viterbi decoding with transpose algorithm
Resource
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers., 1995 International Symposium on
Journal
International Symposium on VLSI Technology, Systems, and Applications, Proceedings
Pages
219 - 223
Date Issued
1995-06
Date
1995-06
Author(s)
DOI
N/A
Abstract
The paper presents a novel transpose path metric (TPM) algorithm to reduce the interconnection routing complexity for radix-2k Viterbi decoder. With simple local interconnections, the algorithm can provide a permutation function for state rearrangement in a transpose strategy. With features of modulation and regularity, this algorithm is very suitable for VLSI implementation; consequently, a larger memory length VA decoder can be constructed with several smaller memory length modules. Finally, a VLSI architecture for 16-states radix-4 VA decoder using TPM has been developed.
Event(s)
Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications
Other Subjects
Algorithms; Computation theory; Computational complexity; Computer architecture; Convolutional codes; Data storage equipment; Decoding; Modulation; Shift registers; VLSI circuits; Decoder; Interconnection routing complexity; Permutation function; Radix; Transpose path metric; Viterbi decoder; Data communication equipment
Type
conference paper
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