Low power design in hardware descr iption language

With the development of nanometer,
more and more gate counts need to be placed
in one chip. Under the performance
requirement, the working frequency of a chip
also increases continually. The following
problems are the power consumption of that
chip, the heat problem and the reliability of
the chip. It is also related to the operating
time of the portable device, while using such
chip on a battery operating system. Most low
power researches on the circuits focus on
optimization the logic blocks. However, there
are lots of data need to be transmitted on the
on-chip buses, and lead to the power
consumption of buses have a high percentage
among total power consumption. Among the
bus problems, there exists a crosstalk problem while two adjacent wires are too
close. It will result in error when data transit,
and also increase the loading of power
consumption and transition delay. Thus, we
proposed a method based on profiling the
switching behavior to solve this problem
efficiently. This method, based on the
profiling information, applying an
architecture that encodes pairs of bus wires,
permutes the wires and assigns an inversion
level to each wire together. Unlike the
previous technique, it can reduce the control
circuit with small delay and area overhead.
As the research results show, it can be
improved about 38.7% of the crosstalk
problem.