A 35-Gb/s limiting amplifier in 0.13um CMOS technology
Journal
2006 Symposium on VLSI Circuits
Pages
122-123
Date Issued
2006-06
Author(s)
Chihun Lee
Abstract
A 35Gb/s limiting amplifier using cascaded-distributed amplifiers with active feedback and on-chip transformers achieves a differential gain S DD21 of 38 dB and a bandwidth of 26.2GHz. It has been fabricated in 0.13mum CMOS technology. It exhibits a single-ended output swing of 300mV PP while consuming 125mW from a 1.5V supply
SDGs
Type
conference paper