Memory efficient JPEG 2000 architecture with stripe pipeline scheduling
Journal
IEEE Transactions on Signal Processing
Journal Volume
54
Journal Issue
12
Pages
4807-4816
Date Issued
2006
Date
2006
Author(s)
Abstract
Memory issues pose the most critical problem in designing a high-performance JPEG 2000 architecture. The tile memory occupies more than 50% area in conventional JPEG 2000 designs. To solve this problem, we propose a stripe pipeline scheduling. It well matches the throughputs and dataflows of the discrete wavelet transform and the embedded block coding to minimize the data lifetime between the two modules. As a result of the scheduling, the overall memory requirements of the proposed architecture can be reduced to only 8.5% compared with conventional architectures. This effectively reduces the hardware cost of the entire system by more than 45%. Besides reducing the cost, we also propose a two-symbol arithmetic encoder architecture to increase the throughput. By use of this technique, the proposed architecture can achieve 124 MS/s at 124 MHz, which is the highest specification in the literature. Therefore, the proposed architecture is not only low cost but also high speed. © 2006 IEEE.
Subjects
Discrete wavelet transform; Embedded block coding with optimized truncation; Image coding; JPEG 2000
Other Subjects
Embedded block coding; Embedded blocks; Optimized truncation; Data flow analysis; Discrete wavelet transforms; Image coding; Logic design; Problem solving; Scheduling; Computer architecture
Type
journal article
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