A Calibration-Free 12-Bit 1.5-GS/s Pipelined ADC With Merged Sub-ADC Quantization Technique
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
72
Journal Issue
9
Start Page
1168-1172
ISSN
1549-7747
1558-3791
Date Issued
2025-09
Author(s)
Abstract
This paper presents a calibration-free 12-bit 1.5-GS/s pipelined ADC employing a merged sub-ADC quantization (MSAQ) technique. Building upon the conventional pipelined ADC architecture, the proposed technique can extend the amplification time, thereby relaxing the design of the inner-stage residue amplifier. A prototype ADC implemented in a 28-nm CMOS technology achieves an SFDR of 70.52 dB and an SNDR of 58.03 dB at a Nyquist input, while consuming 18.5 mW from a 1-V supply. It yields Schreier and Walden figure of merits (FoM) of 164.1 dB and 18.9 fJ/conv.-step, respectively.
SDGs
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article