The effect of NBTI on 3D integrated circuits
Journal
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012 IEEE
Pages
201 - 204
Date Issued
2012-12
Author(s)
Abstract
Thermal-induced reliability problem can be very severe in 3D ICs. In this paper, Negative Bias Temperature Instability (NBTI) effect is addressed. We first propose an NBTI-aware simulation flow for 3D ICs. Using the flow and the MIPS789 benchmark circuit as an example, we demonstrate how we can evaluate digital 3D IC performance under NBTI. By comparing simulation results, we recommend to place critical gates on the layer close to the heat sink in order to lower peak temperature and NBTI impacts. The proposed floor plan can make peak temperature 20 °C lower and NBTI impact 2.4% less when compared to the one using homogeneous stacking.
SDGs
Type
conference paper