Design of a Low-Power Reliable Network-On-Chip Router
Date Issued
2008
Date
2008
Author(s)
Chen, Cheng Chin
Abstract
A scalable hardware router design for Network-on-Chip is proposed in this Thesis. The router is designed with an emphasis on reducing average packet latency and on determining reliability design tradeoffs with respect to a communication-centric and non-deterministic design.he contributions of this router design are threefold. First, the router uses bipartite matching graphs and proposes a set of reductions to reduce the Network-on-Chip allocation problem while retaining the possibility of maximum matching. Next, the router redefines network information for both congestion avoidance and relief purposes by introducing a fluidity concept that can be adapted to many routing and arbitration algorithms. This work also reconsiders the effects of retransmission buffers on energy per useful bit and throughput degradation statistics while presenting a different set of performance tradeoffs geared towards comparing different error correction control schemes. Finally, the hardware router implementation results demonstrate improvements in average packet latency and design for reliability with reasonable increase in overhead.
Subjects
NoC
Network-on-Chip
Router
Fault Tolerance
Type
thesis
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ntu-97-R95943171-1.pdf
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