Segment Weighted Random BIST (SWR-BIST): A Low Power BIST Technique
Part Of
2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Start Page
333
End Page
336
ISBN (of the container)
978-078039162-
Date Issued
2005-11
Author(s)
Event(s)
1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Publisher
IEEE
Type
conference paper