A VLSI architecture of DMT based transceiver for VDSL system
Journal
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
Pages
363-366
Date Issued
2002-08
Date
2002-08
Author(s)
Abstract
This paper presents a VLSI architecture of the transceiver for DMT-VDSL system with data rate as high as 52 Mbps. Consisting of four radix-2 stages and three radix2/4/8 stages, a variable length pipelined architecture of FFT/IFFT compatible with 5 modes is proposed to perform the DMT modulation/demodulation. Based on LMS adaptation algorithm, time domain equalizer (TEQ) and frequency domain equalizer (FEQ) are built. The former makes SSNR > 40dB in the steady-state, while the latter performs 11-bit accuracy. Moreover, timing recovery is adopted to compensate ±200 ppm symbol rate offset. The RTL simulation shows that the design achieves 52 Mbps transmission in short channel model and 16 Mbps for long channel environment. © 2002 IEEE.
SDGs
Other Subjects
Equalizers; Frequency domain analysis; Transceivers; Adaptation algorithms; Frequency-domain equalizers; Pipelined architecture; Rtl simulations; Time-domain equalizers; Timing Recovery; Variable length; VLSI architectures; Computer architecture
Type
journal article
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