Testable Iterative Logic Arrays Based on Scalable and Bijective Cells
Date Issued
2010
Date
2010
Author(s)
Yeh, Po-Yuan
Abstract
In order to achieve testable designs, it is necessary to modify the original designs properly. For different applications, the modifications can be made at either module-level or bit-level circuits to achieve best results. In general, conventional test schemes at module-level or bit-level lead to large number of test patterns (NTP) or significant hardware overhead (HO), respectively. In order to circumvent these problems, we propose a novel test technique to achieve both acceptable NTP and HO by finding a balance between them in this paper.
We propose novel bijective and scalable cells to apply the technique on ILA-based (Iterative Logic Array) architectures. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between HO and NTP, which is a function of n. By adjusting the value n, we can obtain an optimal balance between HO and NTP. The ILAs based on these scalable cells will still be C-testable i.e. testable with constant NTP independent of array size.
Based on the novel bijective and scalable cells, we have several C-testable designs for MAC (Multiplier-Accumulator), N-tap FIR (Finite Impulse Response) filter, matrix multiplication and CORDIC (COordinate Rotation DIgital Computer) design, where the experiments shows that it does achieve better results in comparison with traditional ATPG (Automatic Test Pattern Generation) method. For 4x4 matrix multiplication, the (HO, NTP) pairs with n = 2 are only about (4.87%, 74), and the total test time of the proposed method is only about 0.19% of that with the scan-chain method. For CORDIC design, the (HO, NTP) for n = 2 is (5.37%, 74) by scalable cells and the (HO, NTP) is only (3.15%, 18) by the reorganized test sequences.
It demonstrates that the novel scalable cells bring new advantage for ILA test schemes. It also results in both more reasonable NTP and HO at the same time compared with conventional ILA without scalability. With scalable and bijective cells, all the proposed ILA solutions can be connected together into a bigger non-homogeneous ILA for saving lots of test pins and BIST (Build-In Self Test) area. In addition, the proposed scalable cells induce a simple and systematic way to have balanced results and form new scalable cells. The proposed technique makes ILA-based DFT schemes more practical, systematic and useful for real and complicated applications than existing approaches.
Subjects
C-testable
Design-For-Testability (DFT)
Iterative Logic Array (ILA)
Logic Testing
Scalability
CORDIC (COordinate Rotation DIgital Computer)
Type
thesis
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