A Pico-second Resolution Precise Delay Generator Circuit Using Three Dimension Differential Timing Vernier Mechanism
Date Issued
2004
Date
2004
Author(s)
Chen, Chia-Wei
DOI
en-US
Abstract
As the developments in VLSI system, application frequency is increasing rapidly and more and more data to deal with, so the data processing time have to decrease. The demand for time precision is also increasing. However, the precision time comes from the precision phase, so how to generate the precision phase is more and more important.
In order to increase the resolution of delay time, relative delay is a good choice. This thesis proposes a new architecture using three-dimension delay-locked loop according to differential timing vernier to achieve high resolution relative delay time. Employing control voltage switching to avoid error and jitter come from signal switching. The reference clock of the delay-locked loop is 133MHz, and the loop bandwidth is 20KHz. This high resolution and precision delay generator circuit is fabricated in TSMC 0.18μm CMOS process. The resolution is 15ps and delay range is 50MHz~500MHz. The relative delay time is 0ps~1560ps.
Subjects
延遲鎖定迴路
游標尺
延遲產生器
解析度
三維延遲鎖定迴路
resolution
vernier
delay generator
delay-locked loop (DLL)
3-Dimension delay-locked loop
Type
thesis
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