Multilevel Full-Chip Routing With Testability and Yield Enhancement
Resource
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26 (9): 1625-1636
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal Volume
26
Journal Issue
9
Pages
1625-1636
Date Issued
2007
Date
2007
Author(s)
Type
journal article
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Name
36.pdf
Size
652.95 KB
Format
Adobe PDF
Checksum
(MD5):8cd76680a3e291ecfc537b1ce03fdade
