THERMAL-DRIVEN INTERCONNECT OPTIMIZATION BY SIMULTANEOUS GATE AND WIRE SIZING
Date Issued
2004
Date
2004
Author(s)
Lin, Yi-Wei
DOI
en-US
Abstract
The dramatic increase of power consumption and integration density has led
to high operating temperature. Temperature, as well as electromigration (EM), area,
timing, and power, has become one of the most important concerns in the design
of nanometer integrated circuits. In this thesis, we model the effects of thermal
on both interconnect delay and EM reliability. Applying the least square estimator
(LSE) method, we develop a posynomial formula to approximate interconnect
temperature and present an algorithm that can optimally solve the simultaneous interconnect
temperature, EM, area, delay, and power optimization problem by sizing
circuit components based on Lagrangian relaxation. The experimental results show
that our algorithm can find desired solutions that satisfy all EM reliability requirements
from 11.56% failures among all wires initially. On the average, it improves the
respective area, maximal temperature increase, delay, and power by 11.84%, 10.96%,
70.75%, and 12.01% after wire and gate sizing.
Subjects
連線最佳化
熱效應
interconnect optimization
thermal effects
Type
thesis
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