An efficient embedded bitstream parsing processor for MPEG-4 video decoding system
Journal
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Journal Volume
41
Journal Issue
2
Pages
183-191
Date Issued
2005
Author(s)
Abstract
In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5. © 2005 Springer Science + Business Media, Inc.
Subjects
Bitstream parsing processor; Data partitioned bitstream parsing; MPEG-4; Video decoding
SDGs
Other Subjects
Computer architecture; Computer simulation; Data compression; Data reduction; Optimization; Program processors; Standards; Bitstream parsing processors; Data partitioned bitstream parsing; MPEG-4; Video decoding; Video signal processing
Type
journal article