A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector

Journal

2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Pages

326-329

Date Issued

2004-08

Author(s)

Yang, Rong-Jyi

DOI

10.1109/apasic.2004.1349486

URI

http://scholars.lib.ntu.edu.tw/handle/123456789/310606

http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191002727/1/01349486.pdf

Type

conference paper

File(s)

Name

01349486.pdf

Size

345.22 KB

Format

Adobe PDF

Checksum

(MD5):f256d19a90daf48b8a46ee90e9a29a8c